The present invention relates to a power-on reset circuit for use in a semiconductor device, particularly to a power-on reset circuit for preventing malfunction of a semiconductor device at power-on, and also relates to a semiconductor device having such a power-on reset circuit.
Recent semiconductor devices, which have been sophisticated and systematized, incorporate many functions. In order to have these functions work correctly according to commands from the outside, the commands must be held. A latch circuit such as a flip-flop is mainly used to store command information externally input, and internal circuit operation is controlled according to the stored command information. The latch circuit such as a flip-flop is initialized to a reset state by using a power-on reset signal at power-on to prevent malfunction of the internal circuit. The resetting of the latch circuit at power-on is performed by a circuit called a power-on reset circuit.
However, there are a variety of power-on methods depending on various systems, and they are different in the rising speed of the power source and the manners of change thereof (for example, the power may rise smoothly or stepwise). Therefore, there sometimes occurs a condition that has not been considered in simulation of a circuit for outputting a power-on reset signal. This condition may lead to a phenomenon that resetting cannot be performed properly. Thus, consideration must be given to a case in which the power-on reset signal does not operate properly to reset the latch circuit at power-on. For this purpose, the latch circuit is designed so that it readily becomes a reset state. In this respect, a method is known to adjust transistor sizes to configure a latch circuit such that the circuit is easy to be shifted to a specific direction (an expected value level or reset state at power-on). However, such method is not perfect.
When the power-on reset circuit outputs a latch signal different from an expected value at power-on, the latch circuit is often set to a special kind of mode. For example, if the latch circuit is set to a mode to stop internal power source for power saving, the circuit may be subsequently unable to operate normally (unless the circuit is reset). Moreover, following the increase of the number of functions incorporated in a semiconductor device, the number of latch circuits to latch commands has also been increased to cope with those functions. It becomes important to reliably initialize these many latch circuits to the reset state at power-on. Therefore, there is a demand for a power-on reset circuit that is applicable to a variety of systems without causing malfunction during power-on.
Referring to FIGS. 1 and 2, power-on reset circuits of the related art will be described. FIG. 1 shows a power-on reset circuit having an RS-flip-flop as a latch circuit, and the flip-flop is formed by an NAND circuit. FIG. 2 is a circuit block diagram of the RS-flip-flop 71 in the level of transistors. The flip-flop 71 receives an inverted signal SB of a set signal S7 as set input, and an output signal RB from an NOR circuit receiving a reset signal R7 and a power-on reset signal PON7, as a reset signal, and outputs output 7A. An inverted signal of the output 7A from the flip-flop 71 is a latch signal T7.
In the case of the logical configuration shown in FIG. 1, the power-on reset signal PON7 is a signal that becomes “H” level only during power-on. The reset signal R7 is a reset signal that is generated according to normal (regular) input from the outside. For example, the reset signal R7 may be a mode register set command used in an SDRAM. Therefore, the reset signal R7 remains “L” level during power-on. The power-on reset circuit shown in FIG. 1 resets the flip-flop 71 by the NOR of the reset signal R7 and the power-on reset signal PON7. When the power source rises, the flip-flop 71 is reset by the power-on reset signal PON7 becoming “H” level in a pulsed manner, and the latch signal T7 is set to the expected value, “L” level. The set signal S7 is a signal that is input when the latch signal T7 is to be activated (when the latch signal T7 is to be shifted to “H” level in the case of the logical configuration of FIG. 1).
In the configuration of FIG. 1, it is by the power-on reset signal PON7 that the latch signal T7 is set to the expected value, “L” level at power-on. In the event that no power-on reset signal PON7 is generated, the latch signal T7 will become indefinite. If the latch signal T7 becomes “H” level instead of the expected value, the mode may be set to an unexpected one, causing failure in operation of the internal circuit. In consideration of a case in which no power-on reset signal PON7 is generated, it is also proposed to design the flip-flop 71 such that the flip-flop 71 is readily shifted to the expected value (reset state) at power-on.
FIG. 2 is a circuit block diagram showing the flip-flop 71 in the transistor level. In order to turn the latch signal T7 to the expected value or “L” level at power-on, an output contact 7A must be at “H” level. The output contact 7A can be made easy to be shifted to “H” level at power-on, for example by designing the sizes of transistors such that: the capacity of transistors P1 and P2 is smaller than the capacity of transistors P3 and P4; and the capacity of transistors N1 and N2 is greater than the capacity of transistors N3 and N4. In general, a flip-flop is made symmetrical by balancing the capacities of its inverter circuits. However, this flip-flop is made asymmetrical and designed such that one of the output levels is easier to output at power-on. When the flip-flop is made to output one of the output levels, for example “H” level more easily, it is represented that the flip-flop is made easy to be shifted to “H” level.
The capacity setting for the transistors in this case are adjusted in such a manner that, in order to increase the capacity of a transistor, for example, the channel width of the transistor is set relatively large or the channel length is set relatively short. Thus, the power-on reset signal generated at power-on and the sizes of the transistors in the latch circuit are devised so as to avoid malfunction during power-on. However, when such a latch circuit is practically used in various systems, these measures sometimes are not valid to solve the problems, resulting in failure of resetting. Therefore, there is a demand for a power-on reset circuit having simple configuration and yet capable of reliably realizing an expected value.
The power-on resetting at power-on is described in prior patent publications as follows. Japanese Laid-Open Patent Publication NO. H08-111089 (Patent Publication 1) describes a technique in which the resetting is performed by generating a new power-on reset signal having a long pulse width from a precharged signal and a normal power-on reset signal. This new power-on reset signal having a long pulse width eliminates the effect of the rising up of the power source. Japanese Laid-Open Patent Publication NO. 2001-273054 (Patent Publication 2) describes a technique in which initialization at power-on is performing by monitoring and setting the output value of a latch circuit so as to prevent the through current. The power-on resetting techniques as described in the prior patent publications above are not applicable universally. Therefore, there is a demand for a power-on reset circuit having simple configuration and yet capable of realizing an expected value (reset state) more reliably.